Programmable logic devices (“PLDs”) (also sometimes referred to as CPLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, FPGAs, or by other names), are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits. Such devices typically provide an “off the shelf” device having at least a portion that can be electrically programmed to meet a user's specific needs. Application specific integrated circuits (“ASICs”) have traditionally been fixed integrated circuits, however, it is possible to provide an ASIC that has a portion or portions that are programmable; thus, it is possible for an integrated circuit device to have qualities of both an ASIC and a PLD. The term PLD as used herein will be considered broad enough to include such devices.
PLDs may include blocks of logic elements (“LE”s), sometimes referred to as logic array blocks (“LABs”; also referred to by other names, e.g., “configurable logic blocks,” or “CLBs”). LEs typically include components that carry out arithmetic logic functions and other components that carry out non-arithmetic logic functions. As used herein, arithmetic logic functions indicates functions including, without limitation, addition, subtraction, multiplication, division and comparison. Non-arithmetic logic functions include, without limitation, Boolean logic functions such as AND, OR, XOR, NOR and NOT.
Often, the arithmetic logic functions in a logic cell are carried out by a look up table (LUI), but can also be carried out by other elements such as product terms, carry-out chains, registers, and other elements. The LUT is typically followed by one or more logic gates and/or multiplexers.
To carry out a desired logic operation, it is often the case that an LE will be configured in an arithmetic logic mode to carry out an arithmetic logic function. An output form the LE will then drive a block of non-arithmetic logic to complete the logic operation. Often, the logic operation will require more non-arithmetic logic gates than those available to the single LE. In such a case, the non-arithmetic logic blocks available to other LEs can typically be used. However, this can be inefficient if the arithmetic logic operator of the other LEs are not usable by themselves (that is, without needing to use the non-arithmetic logic block available to the same LE) to carry out necessary arithmetic logic. In such a case, just the non-arithmetic logic blocks available to one or more LEs might be used, thus taking up more space in a PLD than is desirable.